This application claims the priority benefit of Taiwan application serial no. 90126667, filed Oct. 29, 2001.
1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a metal oxide semiconductor field effect transistor (MOSFET) structure with reduced junction capacitance.
2. Description of the Related Art
During a MOSFET device functions, the parasitic junction capacitance of a source/drain region is created at two sides of the depletion region between the source/drain region and the substrate. The junction capacitance is approximately proportional to the area of the source/drain region. The junction capacitance has an adverse effect on the switching speed of a transistor during a logic transition. This is because the junction capacitance will be charged and discharged when each time the transistor switches between logic states, unfavorably slowing down the performance of the transistor.
FIG. 1 depicts a schematic top view of a conventional MOSFET device 18, showing a straight gate electrode 11, symmetric source/drain regions 12 and 13 formed in an active area 17. A plurality of contacts 14 and 15 can be formed above the source/drain regions 12 and 13, respectively.
Still referring to FIG. 1, a dash line 16 shown in the gate electrode 11 represents the width of a channel under the gate electrode 1, while a distance between the source/drain regions 12 and 13 is named as the channel length (not indicated). In this case, the channel width determines the flux of the channel current generated between the source/drain regions 12 and 13. That is, if the channel width becomes smaller as the device is miniaturized, the channel current between the source/drain regions 12 and 13 decreases during an operation, therefore the performance of the device is worse.
Accordingly, it is an object of the present invention to provide a semiconductor device structure having shrunken source/drain regions so that the junction capacitance can be reduced and the performance of the device can also be improved.
It is another object of the present invention to provide a semiconductor device structure having larger channel width so that the channel current will increase during an operation to improve the performance of the device.
It is a further object of the present invention to provide a semiconductor device structure having shrunken source/drain regions so that the integration of the device can be effectively increased.
According to the objects of the present invention mentioned above, the present invention provides a MOSFET structure comprising a tortuous gate and smaller and asymmetric source/drain regions.
Specifically, the present invention provides a MOSFET structure, comprising a tortuous gate having a first sidewall and a second sidewall, disposed over a semiconductor substrate. A source region is disposed within the semiconductor substrate adjacent to the first sidewall of the tortuous gate. The source region comprises a broader part and a narrower part. Contacts are positioned above the broader part of the source region and are electrically contacted with the broader part of the source region. A drain region is disposed within the semiconductor substrate adjacent to the second sidewall of the tortuous gate. The drain region comprises a broader part and a narrower part. Contacts are disposed above the broader part of the drain region and are electrically contacted with the broader part of the drain region. The broader part of the drain region is disposed opposite to the narrower part of the source region. The narrower part of the drain region is disposed opposite to the broader part of the source region.
In accordance to an aspect of the present invention, a MOSFET device having a tortuous gate structure is provided. Because of the tortuous gate structure, there is a broader part of the source region disposed opposite to a narrower part of the drain region and there is a narrower part of the source region disposed opposite to a broader part of the drain region. Since the area of the broader part of the source/drain region with contacts on it can be close to the corresponding part of a source/drain in the conventional MOSFET and the area of the narrower part of the source/drain region without contact on it can be further reduced, the source and drain region of the device of the present invention can be smaller compared to the conventional MOSFET structure. In other words, asymmetric source/drain regions with smaller areas can be formed. This makes it possible to further reduce the junction capacitance. And the size of the MOSFET device can be reduced, thereby increasing the integration of the IC device.
Another aspect of the present invention is that because of the tortuous gate structure of the present invention, contacts are disposed only on the broader part of the source/drain regions. The area needed for a conductive layer electrically connecting with the contacts over the MOSFET can be smaller compared to the conventional MOSFET structure. Thus the integration of the IC device can be increased.
Yet another aspect of the present invention is that because of the tortuous gate, the channel width can be effectively increased. Because the channel width is increased, the channel current is larger. Thus the performance of the MOSFET device can be substantially enhanced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.